1. Field of the Invention
The present invention relates to a semiconductor device having a multilayer wiring structure, and to a method for manufacturing the same.
2. Description of Related Art Japanese Patent Laid-Open Publication No. 2008-047734 describes a System In Package (SIP)-type semiconductor package (semiconductor device) in which a plurality of semiconductor chips are embedded. As described in No. 2008-047734, two insulating layers (6, 7) are stacked on a substrate (1) on which a circuit is not formed, wires (9, 13) are patterned on the individual insulating layers (6, 7), a bare chip (5) is embedded in the insulating layer (6) as a lower layer, further, a thick buffer layer (17) is stacked on the insulating layers (6, 7) as upper layers, and another bare chip (16) protected only by a silicon oxide film (16d) is embedded in the buffer layer (17).
In such a technology described in Japanese Patent Laid-Open Publication No. 2008-047734, the chips (5, 13) are embedded in the insulating layer (6) and the buffer layer (17), which are stacked on the substrate (1). Accordingly, the semiconductor package is thickened.
Moreover, the substrate (1) is a substrate obtained by cutting a wafer into pieces. After the chip (5) is mounted on the wafer, the wafer is finally cut. Accordingly, a size of the substrate (1) as the cut piece becomes larger than a size of the chip (5). Therefore, a size of the semiconductor package is enlarged.